Phase-locked loops are used in a variety of applications. In general, phase-locked loops include a phase comparator or phase detector to compare the phase of a frequency-divided output signal of the voltage controlled oscillator and a reference signal. The difference between these two signals is used to generate a control signal or error signal, which is fed back to the voltage controlled oscillator so as to control the frequency of its signal output in a direction that reduces this phase difference. For example, phase-locked loops are used in different types of radio systems, such as cellular phones, in which an oscillator is locked to an accurate reference frequency. Different means are then provided to scale this accurate reference frequency to the desired frequency.
In a conventional phase-locked loop (PLL) it is well known to divide the output signal of the voltage controlled oscillator (VCO) by a natural number. The division may be performed by a divider or frequency divider. The reason to perform the division is because comparators according to the prior art only are able to compare the phase of two signals if the frequency of the two signals to be compared are equal and because the output frequency usually is “high” (MHz or GHz range) it is easier/more feasible to have the control circuit to work at a lower frequency. In some embodiments the reference clock may also be divided by a natural number by a frequency divider in order to obtain a given frequency of the two signals to be compared.
When using a conventional phase-locked loop some unwanted frequency components or spurious occur in the output signal. These spurious occur as a result of the phase comparator (also called phase detector) working at a frequency given hereby. The spurious are an unwanted effect as it most often reduces the overall performance of the system in which the phase-lock loop is operating. For example, spurious on the carrier in a radio system is a disadvantage as it causes undesired channels to interfere with the desired channel and thereby reducing the over-all performance of the radio system.
According to the prior art, a solution to this problem is to filter out the spurious by use of a loop filter, most often located between the phase comparator and the voltage-controlled oscillator, i.e. the control signal for the voltage-controlled oscillator is filtered. Generally the spurious can be filtered out in a loop filter if the bandwidth of the loop filter is significantly small, e.g. smaller than the distance between the spurious. But the price of reducing the bandwidth of the loop filter is a slower PLL, i.e. the lock-in time for the PLL is increased.
Some if not most prior art phase-locked loops, which are fully or partly implemented using digital components, also have a risk of producing sub-harmonic frequencies due to the way they are implemented. This is due to the way the two signals, the reference signal and the output signal, interact with each other. Ideally the reference signal and the output signal operates asynchronous, where the phase lock is established when the phases coincide. Until this happens and if a disturbance breaks the lock there may occur sub-harmonics.
U.S. Pat. No. 5,459,435 shows a digital implementation of a PLL. The invention is a straight forward conversion of the known analog PLL topology, where a first and a second counter unit is used to indicate the phase error between the frequency divided output signal and the reference. The resolution of the PLL is fixed to the bit resolution of the digital implementation thus fixing the ratios between output frequency and reference frequency.
U.S. Pat. No. 5,999,060 also shows a digital implementation of a PLL using counters. As with U.S. Pat. No. 5,459,435 the resolution of the PLL is firstly fixed to the bit resolution, but is secondly compensated by a scaling means in the feed back. The scaling means gives the possibility to increase the number of possible output frequencies.
U.S. Pat. No. 6,188,288 is similar in many ways to U.S. Pat. No. 5,999,060 in that some scaling means is used in the feed back to compensate for the bit resolution. U.S. Pat. No. 6,188,288 differs from the above mentioned PLL's in that a current controlled oscillator is used and not a voltage controlled oscillator.
The above mentioned PLL introduces means for increasing the number of possible output frequencies. They also increase the complexity of the PLL-circuit considerably and do not improve on the lock-in time for the PLL, because a loop filter with a narrow bandwidth is still needed.
In U.S. Pat. No. 6,046,643 is described a digital implementation of a PLL circuit. Here, a frequency divider with a fixed division rate has the output of the voltage controlled oscillator as input, and the output of the divider supplies a first clock signal to a first accumulator, which aggregates a first reference signal under control of the first clock signal. A second accumulator aggregates a second reference signal under the control of the reference clock signal. The aggregated signals are subtracted from one another, filtered through a digital filter, weighted and then converted into an analogue signal, This analogue signal is filtered by an analogue filter and fed to the voltage controlled oscillator. Thus, the difference between the two aggregated signals may be used for generating a control or error signal for controlling the frequency of the voltage controlled oscillator in a direction to reduce the difference between the two aggregated signals, and the output frequency may be selected by a suitable selection of the first and second reference signals. However, the two aggregated signals from the two accumulators are asynchronous signals, thereby generating a problem for the subtraction process. In U.S. Pat. No. 6,046,643 there is nowhere giving a solution for performing such a subtraction of two asynchronous signals, except for the filtering processes following the subtraction.